Gettering is a technique used during semiconductor device fabrication process to remove impurities from the active device areas. The impurities include metallic impurities such as, for example, iron, gold, nickel and copper. These metallic impurities create deep level traps inside the semiconductor band gap that act as generation-recombination sites. It is well known that these sites result in the degradation of semiconductor device performance. In particular, they result in increased dark current and defective pixels in image sensor devices.
Gettering methods are commonly used in semiconductor device processing to remove unwanted metallic impurities. These metallic impurities are incorporated in the semiconductor lattice during production of semiconductor substrates or wafers such as Czochralski ingot pulling or epitaxial growth. A variety of gettering techniques are known and used.
One set of methods involve creating a gettering site at or near the backside of the semiconductor substrates where circuit devices are not planned to be formed. These methods include intentionally creating damage through ion implantation or deposition of metal films that act as a sink for metallic impurities. These methods do not work for slow diffusing impurities or require very long processing times and high thermal budgets since the metal impurities have to travel through the entire wafer thickness to get to the gettering sites. Moreover, these methods are not effective for silicon on insulator (SOI) type wafers where the buried oxide layer acts as a diffusion barrier.
Another set of gettering methods use “proximity gettering” and involve creating gettering sites close to the region where devices are located. These methods overcome some of the problems listed above for the methods that use backside damage. Such methods are described in U.S. Pat. No. 6,509,248, U.S. Pat. No. 7,470,944, and U.S. Pat. No. 5,453,385.
The method proposed in U.S. Pat. No. 5,453,385 uses oxide growth to remove the gettering sites formed below LOCOS structures. This has the disadvantage that some impurities cannot be incorporated in the oxide but instead remain inside the silicon as the oxide is grown. Also, LOCOS isolation has become obsolete in a number of semiconductor processes and has been replaced by other isolation techniques such as trench isolation.
U.S. Pat. No. 6,509,248 discloses the use of ion implantation through previously etched trench isolation structures to form gettering sites relatively deep inside the semiconductor substrates. However, since the gettering sites are not removed from the wafer, some of the metal impurities become un-gettered during the high temperature steps used for device fabrication. Also, metal impurities located at the gettering sites generate charged carriers that can reach the active area of devices. To prevent these charges from reaching the devices, U.S. Pat. No. 7,470,944 proposes contacting the gettering site so that a transport path for the charge is formed. This however requires complicated processing with addition of multiples extra steps. Also, control of the gettering site size has to be very precise so that it doesn't extend to the device active area.